- 門(mén)信號(hào)延遲
- 門(mén)延遲
- 選通延遲
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gate delay中文什么意思
例句與用法
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- Trigger gate delay
觸發(fā)門(mén)脈沖延遲 - The problem in high speed signal process , such as parasitic parameter and gate delay is also the difficulty hi the research
生成高速，穩(wěn)定的時(shí)鐘信號(hào)是本課題的目標(biāo)。高速信號(hào)處理所遇到的常見(jiàn)問(wèn)題，如寄生參數(shù)，門(mén)電路延遲是設(shè)計(jì)難點(diǎn)。 - Due to the subtle error among different manufacturing equipment , the gate delay of circuits is different and varies in a given scope , which induces the time uncertainty of the waveform
由于制造設(shè)備本身存在微小誤差，具體門(mén)的延時(shí)并不相同，而是在一定范圍內(nèi)變化，引起波形變化的時(shí)間不確定。 - This paper constructs a stable rlc interconnect model based on the first three moments of the node admittance , and discusses its application to interconnect delay and logic gate delay estimation
摘要基于rlc互連樹(shù)節(jié)點(diǎn)導(dǎo)納的低階矩構(gòu)建了一種穩(wěn)定的互連模型，并討論了它在互連樹(shù)延時(shí)和邏輯門(mén)延時(shí)估計(jì)中的應(yīng)用。 - When the silicon technology comes to deep sub - micron level , the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency , the allowable errors become smaller , and the influence of the transmission delay gets bigger , which increase the difficulty of the circuit design
在深亞微米制造技術(shù)中，芯片互連線(xiàn)延遲超過(guò)門(mén)延遲，而且隨著集成電路工作頻率的提高，允許的時(shí)序容差變小，傳輸延遲的影響加大，設(shè)計(jì)工作難度增加。